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A Hardware Architecture for Surface Splatting
ACM Transactions on Graphics (Proc. SIGGRAPH), August 2007

Tim Weyrich, Simon Heinzle, Timo Aila,
Daniel B. Fasnacht, Stephan Oetiker, Mario Botsch,
Cyril Flaig, Simon Mall, Kaspar Rohrer,
Norbert Felber, Hubert Kaeslin, Markus Gross


Point rendering system featuring an ASIC implementation of our point rendering architecture. The system runs standalone, independent from a host PC.

Abstract

We present a novel architecture for hardware-accelerated rendering of point primitives. Our pipeline implements a refined version of EWA splatting, a high quality method for antialiased rendering of point sampled representations. A central feature of our design is the seamless integration of the architecture into conventional, OpenGL-like graphics pipelines so as to complement triangle-based rendering. The specific properties of the EWA algorithm required a variety of novel design concepts including a ternary depth test and using an on-chip pipelined heap data structure for making the memory accesses of splat primitives more coherent. In addition, we developed a computationally stable evaluation scheme for perspectively corrected splats. We implemented our architecture both on reconfigurable FPGA boards and as an ASIC prototype, and we integrated it into an OpenGL-like software implementation. Our evaluation comprises a detailed performance analysis using scenes of varying complexity.

Citation (BibTeX)

Tim Weyrich, Simon Heinzle, Timo Aila, Daniel B. Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, and Markus Gross. A Hardware Architecture for Surface Splatting. ACM Transactions on Graphics (Proc. SIGGRAPH) 26(3), August 2007.

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